Shared load-store unit to monitor network activity and external memory transaction status for thread switching

摘要

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

主权项

1. A method for facilitating thread switching in a multi-processor system comprising a plurality of processing elements and a plurality of local memories coupled together by a packet-switched interconnection network, which includes a plurality of network nodes and an end node coupled to an external memory, the method comprising:
using a shared load-store unit to monitor activity on the network by monitoring activity flags in the network nodes to determine whether activity on the network has ceased and that an external memory transaction has passed beyond the end node to the external memory; using the shared load-store unit to monitor transaction-enable flags in the processing elements that indicate whether results of the external memory transaction have returned to the processing elements; and upon determining that activity on the network has ceased and that one or more transaction-enable flags remain enabled, determining that the external memory transaction remains in progress, and indicating to a controller that a thread switch may take place.