发明名称 Graphics power control with efficient power usage during stop
摘要 In an embodiment, a processor that includes multiple cores may implement a power/performance-efficient stop mechanism for power gating. One or more first cores of the multiple cores may have a higher latency stop than one or more second cores of the multiple cores. The power control mechanism may permit continued dispatching of work to the second cores until the first cores have stopped. The power control mechanism may prevent dispatch of additional work once the first cores have stopped, and may power gate the processing in response to the stopping of the second cores. Stopping a core may include one or more of: requesting a context switch from the core or preventing additional work from being dispatched to the core and permitting current work to complete normally. In an embodiment, the processor may be a graphics processing unit (GPU).
申请公布号 US9035956(B1) 申请公布日期 2015.05.19
申请号 US201213466622 申请日期 2012.05.08
申请人 Apple Inc. 发明人 Schreyer Richard W.;Jane Jason P.;Swift Michael J. E.;Avkarogullari Gokhan;Semeria Luc R.
分类号 G06T1/60 主分类号 G06T1/60
代理机构 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. 代理人 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. ;Merkel Lawrence J.
主权项 1. A method comprising: determining that a graphics processing unit (GPU) is to be powered down, wherein the GPU comprises at least a first processing unit and a second processing unit, and wherein both of the first processing unit and the second processing unit are to be powered down to power down the GPU; responsive to the determining, monitoring the first processing unit to detect a stop in the first processing unit; continuing to issue commands to the second processing unit until detecting that the first processing unit has stopped; responsive to detecting the stop by the first processing unit, requesting that the second processing unit stop; and powering down the GPU responsive to the second processing unit stopping.
地址 Cupertino CA US