发明名称 TIMING ADJUSTMENT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a timing adjustment circuit that allows generating a timing-adjusted output signal without the occurrence of malfunction even when an input clock signal is speeded up, and to provide a semiconductor integrated circuit device.SOLUTION: A timing adjustment circuit includes: a voltage-controlled delay line 1 receiving an input clock signal CLK and generating a multiphase clock in which a delay amount is changed on the basis of a control voltage Vcntl; a phase detector 3 detecting a phase difference between a first clock REF to be a reference and a second clock FB from the voltage-controlled delay line 1; control voltage generation circuits 4 and 5 generating the control voltage Vcntl on the basis of the detected phase difference; and a start-up circuit 7 operating for only a certain period of time after start-up and continuously changing the control voltage Vcntl between a first voltage GND and a second voltage VDD.
申请公布号 JP2015095860(A) 申请公布日期 2015.05.18
申请号 JP20130235911 申请日期 2013.11.14
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 MATSUDA ATSUSHI
分类号 H03L7/10;H03K5/135;H03L7/081 主分类号 H03L7/10
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