发明名称 LOGIC CIRCUIT, LOGIC CIRCUIT LAYOUT SUPPORT DEVICE, LOGIC CIRCUIT LAYOUT SUPPORT METHOD AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a logic circuit capable of preventing wasteful power consumption from increasing by removing glitch which cannot be completely eliminated by a glitch elimination circuit.SOLUTION: The logic circuit 100, inputting input data and a clock signal into a flip-flop 1 and a timing generation circuit 6, includes a glitch elimination circuit 4 for eliminating glitch, provided between combined circuits 2 of the logic circuit 100, and a latch circuit 8 for eliminating glitch which cannot be completely eliminated by the glitch elimination circuit 4 with an output of the timing generation circuit 6 input.
申请公布号 JP2015095786(A) 申请公布日期 2015.05.18
申请号 JP20130234534 申请日期 2013.11.13
申请人 MITSUBISHI ELECTRIC CORP 发明人 SAEKI MINORU
分类号 H03K5/1252;G06F17/50 主分类号 H03K5/1252
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