发明名称 SYSTEMS AND METHODS FOR VOID REDUCTION IN A SOLDER JOINT.
摘要 <p>In accordance with one or more aspects, a method of reducing void formation in a solder joint may comprise applying a solder paste deposit to a substrate, placing a solder preform in the solder paste deposit, disposing a device on the solder preform and the solder paste deposit, and processing the solder paste deposit and the solder preform to form the solder joint between the device and the substrate. In some aspects, the substrate is a printed circuit board and the device is an integrated circuit package.</p>
申请公布号 MX2014003639(A) 申请公布日期 2015.05.15
申请号 MX20140003639 申请日期 2012.09.25
申请人 ALPHA METALS, INC. 发明人 PAUL J., KOEP;ELLEN S., TORMEY;DE MONCHY, MICHIEL
分类号 H05K3/34 主分类号 H05K3/34
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