| 发明名称 |
NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST |
| 摘要 |
A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element. |
| 申请公布号 |
US2015131364(A1) |
申请公布日期 |
2015.05.14 |
| 申请号 |
US201314077263 |
申请日期 |
2013.11.12 |
| 申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
HSIEH Wei-jer;LIN Yangsyu;LU Hsiao Wen;CHENG Chiting;CHANG Jonathan Tsung-Yung |
| 分类号 |
G11C7/12;G11C11/419 |
主分类号 |
G11C7/12 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A device comprising:
a transistor switch coupled between a bit line voltage node and a ground node; a boost signal circuit coupled to a gate node of the transistor switch, the boost signal circuit providing a boost signal responsive to a write enable signal; a first delay element; a first capacitor m series with the first delay element and having a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element, a second delay element; and a second capacitor in series with the second delay element and having a first end coupled to the bit line voltage node and a second end coupled to second end of the first capacitor through the second delay element. |
| 地址 |
Hsin-Chu TW |
