发明名称 SYSTEM AND METHOD OF SELECTIVELY APPLYING NEGATIVE VOLTAGE TO WORDLINES DURING MEMORY DEVICE READ OPERATION
摘要 PROBLEM TO BE SOLVED: To provide systems and methods of selectively applying negative voltage to word lines during memory device read operation, with reduced leakage current, improved operation at lower operating voltages, and reduced power consumption in a memory array.SOLUTION: A memory device includes a word line logic circuit 110 coupled to a plurality of word lines 108 and adapted to selectively apply a positive voltage V to a selected word line coupled to a selected memory cell that includes a magnetic tunnel junction (MTJ) device and to apply a negative voltage NV to unselected word lines.
申请公布号 JP2015092431(A) 申请公布日期 2015.05.14
申请号 JP20140258034 申请日期 2014.12.19
申请人 QUALCOMM INCORPORATED 发明人 SEI SEUNG YOON;ZHONG CHENG;PARK DONGKYU;MOHAMED H ABU-RAHMA
分类号 G11C11/15 主分类号 G11C11/15
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