发明名称 SEMICONDUCTOR MODULE INSPECTION METHOD AND SEMICONDUCTOR SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To evaluate the state of a junction of a semiconductor module at short time.SOLUTION: In a semiconductor module inspection method, a capacitance between any terminals of a P terminal 6, N terminal 7, and AC terminal 8 which connect a circuit constituted of semiconductor chips 2-5 with external circuits, and parasite resistance that parasites in series to the capacitance are measured; and the degree of deterioration in junctions (junctions at solder layer 12, 14, and 16, and wires 13 and 15) of a semiconductor module 1 on the basis of secular changes of the measured capacitance and/or parasite resistance is evaluated. In addition, a cooler terminal 11a is provided in a cooler 11 which is provided in a base 10 of the semiconductor module 1 via a grease layer 17; a capacitance between the cooler terminal 11a and any terminal of the P terminal 6, N terminal 7, and AC terminal 8, and parasite resistance parasitic in series to the capacitance are measured; and the degree of deterioration in the grease layer 17 between the base 10 and cooler 11 is evaluated on the basis of the measured capacitance and/or parasite resistance.</p>
申请公布号 JP2015092140(A) 申请公布日期 2015.05.14
申请号 JP20130231640 申请日期 2013.11.08
申请人 MEIDENSHA CORP 发明人 NISHIGUCHI TETSUYA;YAMADA SHINICHI
分类号 G01R31/26;H01L25/07;H01L25/18 主分类号 G01R31/26
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