Chip-on-Wafer Structures and Methods for Forming the Same

摘要

A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

主权项

1. A device comprising:
a package component comprising a substrate; a through-via penetrating through the substrate; a conductive feature over a first surface of the package component and electrically coupled to the through-via; a polymer comprising a first portion contacting a sidewall of the substrate, and a second portion overlapped by the package component; and a first dielectric pattern comprising:
a first portion over and aligned to the polymer; anda second portion over the substrate and vertically misaligned with the polymer.