| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory device which can reduce a charge trap of non-volatile memory cells while suppressing an increase in chip area and in load capacity, and the like.SOLUTION: A memory device includes non-volatile memory cells M11, M12, etc., capable of electrical writing and erasing data and a transistor TN. A word line WS1 of the MONOS type non-volatile memory cells M11, M12, etc., and a gate electrode GT of the transistor TN are formed of common conductive wiring PL. A contact CNA for supplying a voltage to the word line WS1 and the gate electrode GT is formed on the conductive wiring PL. As viewed in a plan view, a channel region of the transistor TN is formed in a route of the conductive wiring PL among the contact CNA and the non-volatile memory cells M11, M12, etc. When a length of the channel region of the transistor TN is represented by D1, and a distance from a contact side end portion of the channel region to the contact CNA is represented by D2, D1 and D2 satisfy an equation of D2<D1. |
