| 发明名称 |
INDUCING LOCALIZED STRAIN IN VERTICAL NANOWIRE TRANSISTORS |
| 摘要 |
A device includes a semiconductor substrate and a vertical nano-wire over the semiconductor substrate. The vertical nano-wire includes a bottom source/drain region, a channel region over the bottom source/drain region, and a top source/drain region over the channel region. A top Inter-Layer Dielectric (ILD) encircles the top source/drain region. The device further includes a bottom ILD encircling the bottom source/drain region, a gate electrode encircling the channel region, and a strain-applying layer having vertical portions on opposite sides of, and contacting opposite sidewalls of, the top ILD, the bottom ILD, and the gate electrode. |
| 申请公布号 |
US2015129831(A1) |
申请公布日期 |
2015.05.14 |
| 申请号 |
US201514599247 |
申请日期 |
2015.01.16 |
| 申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Colinge Jean-Pierre;Chang Gwan Sin;Diaz Carlos H. |
| 分类号 |
H01L29/06;H01L29/78;H01L29/10 |
主分类号 |
H01L29/06 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A device comprising:
a semiconductor substrate; a vertical nano-wire over the semiconductor substrate, the vertical nano-wire comprising:
a bottom source/drain region;a channel region over the bottom source/drain region; anda top source/drain region over the channel region; a top Inter-Layer Dielectric (ILD) encircling the top source/drain region; a bottom ILD encircling the bottom source/drain region; a gate electrode encircling the channel region; and a strain-applying layer comprising vertical portions on opposite sides of, and contacting opposite sidewalls of, the top ILD, the bottom ILD, and the gate electrode. |
| 地址 |
Hsin-Chu TW |
