发明名称 |
Wafer-Level Chip Scale Package |
摘要 |
A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction. |
申请公布号 |
US2015129892(A1) |
申请公布日期 |
2015.05.14 |
申请号 |
US201414290719 |
申请日期 |
2014.05.29 |
申请人 |
DELTA ELECTRONICS, INC. |
发明人 |
LEE Chia-Yen;LIN Chi-Cheng;TSAI Hsin-Chang |
分类号 |
H01L23/48;H01L29/20 |
主分类号 |
H01L23/48 |
代理机构 |
|
代理人 |
|
主权项 |
1. A wafer-level chip scale package, comprising:
a semiconductor chip comprising a transistor formed therein; a first dielectric layer disposed on the semiconductor chip; a first redistribution trace disposed on the first dielectric layer and electrically connected with a first electrode of the transistor; a second dielectric layer disposed on the first redistribution trace; a first via disposed in the second dielectric layer and coupled with the first redistribution trace; and a first pad disposed on the second dielectric layer and electrically connected with the first redistribution trace through the first via; wherein the first redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction. |
地址 |
Taoyuan Hsien TW |