| 摘要 |
A data processing apparatus, a data processing method and a computer program product are disclosed. The data processing apparatus comprises: a processor comprising a plurality of parallel lanes for parallel processing of sets of threads, each lane comprising a plurality of pipelined stages, the pipelined stages of each lane being operable to process instructions from the sets of threads; and scheduling logic operable to schedule instructions for processing by the lanes, the scheduling logic being operable to identify that one of the sets of threads being processed is to be split into a plurality of sub-sets of threads and to schedule at least two of the plurality of sub-sets of threads for processing by different pipelined stages concurrently. In this way, when a thread set is split into sub-sets of threads, rather than waiting for each sub-set to be completely executed to a reconvergence point, instead multiple sub-sets may be scheduled for processing by separate pipelined stages at the same time. This enables the sub-sets to be processed more quickly and enables reconvergence to be reached more rapidly than would otherwise be possible. |
