MULTI-LEVEL CELLS AND METHOD FOR USING THE SAME

摘要

The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.

主权项

1. A method for detecting individual resistance states of a plurality of memory elements coupled in series in a memory device, each of the plurality of memory elements having a resistance state and can be switched from a first resistance level to a second resistance level by a write input no lower than a write threshold, the method comprising the steps of:
sequentially writing at least one of the plurality of memory elements from the resistance state thereof to the second resistance level in order of ascending write threshold; ascertaining whether each of the at least one of the plurality of memory elements has switched from the first resistance level to the second resistance level; concluding the resistance state of the each of the at least one of the plurality of memory elements is in the first resistance level if the each of the at least one of the plurality of memory elements has switched; and concluding the resistance state of the each of the at least one of the plurality of memory elements is in the second resistance level if the each of the at least one of the plurality of memory elements has not switched.