发明名称 MECHANISMS TO ACCELERATE TRANSACTIONS USING BUFFERED STORES
摘要 In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
申请公布号 US2015134896(A1) 申请公布日期 2015.05.14
申请号 US201414536805 申请日期 2014.11.10
申请人 Intel Corporation 发明人 ADL-TABATABAI ALI-REZA;NI YANG;SAHA BRATIN;BASSIN VADIM;SHEAFFER GAD;CALLAHAN DAVID;GRAY JAN
分类号 G06F12/08;G06F9/46 主分类号 G06F12/08
代理机构 代理人
主权项 1: A method comprising: executing a transactional memory (TM) transaction of an atomic section of code in a first thread within a processor; during the TM transaction, buffering a block of data in a first buffer of a cache memory of the processor responsive to determining that the block of data is sized to fit within the first buffer; and executing a first write barrier operation to acquire a write lock and a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated.
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