Semiconductor Device and a Method of Manufacturing the Same

摘要

A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

主权项

1. A method for manufacturing a semiconductor device including a first MISFET of an n-type and a second MISFET of a p-type, comprising steps of:
(a) forming a trench in a semiconductor substrate; (b) embedding an insulating film in the trench to form an element isolating region for dividing the first and second MISFETs; (c) forming a first gate electrode of the first MISFET over the semiconductor substrate; (d) forming a second gate electrode of the second MISFET over the semiconductor substrate; (e) forming a first film including silicon and nitrogen over the first MISFET, the second MISFET and the element isolating region to cover the first and second gate electrodes; (f) after the step (e), forming a second film including silicon and oxygen over the first film; (g) after the step (f), selectively etching the first and second films of the second MISFET, so that ends of the first and second films are located over the element isolating region; (h) after the step (g), forming a third film including silicon and nitrogen over the first MISFET, the second MISFET and the element isolating region to cover the first and second gate electrodes; and (i) after the step (h), selectively etching the third film of the first MISFET by using the second film as an etching stopper for protecting the first film of the first MISFET, so that an end of the third film is located over the element isolating region.