发明名称 Clocking for pipelined routing
摘要 An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers."
申请公布号 EP2871550(A1) 申请公布日期 2015.05.13
申请号 EP20140186552 申请日期 2014.09.26
申请人 ALTERA CORPORATION 发明人 GALLOWAY, DAVID;LEWIS, DAVID;FUNG, RYAN;MANOHARARAJAH, VALAVAN;CHROMCZAK, JEFFREY CHRISTOPHER
分类号 G06F1/10 主分类号 G06F1/10
代理机构 代理人
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