发明名称 信号処理装置
摘要 <p><P>PROBLEM TO BE SOLVED: To suppress deterioration in SN ratio while reducing the number of wires connecting two chips. <P>SOLUTION: A first chip 10 comprises a noise shaper 14 for converting second data D2 into 1-bit third data D3 and a PDM transmission circuit 15 which transmits a transmission signal YPDM via first signal wiring L1 and transmits a clock signal YCLK via second signal wiring L2. A second chip 20 comprises a moving average filter 22 for converting the third data D3 into 6-bit data, a clip circuit 24 for outputting 5-bit fifth data D5, and a DEM-DAC 25. <P>COPYRIGHT: (C)2013,JPO&INPIT</p>
申请公布号 JP5716521(B2) 申请公布日期 2015.05.13
申请号 JP20110101718 申请日期 2011.04.28
申请人 发明人
分类号 H03M1/86 主分类号 H03M1/86
代理机构 代理人
主权项
地址