发明名称 |
METHOD AND GATE RUCTURE FOR THRESHOLD VOLTAGE MODULATION IN TRANSISTORS |
摘要 |
The present invention provides a structure capable of controlling a threshold voltage of N and P channel transistors independently and a manufacturing method thereof. The manufacturing method of a semiconductor device according to the technology comprises the steps of; preparing a substrate including a PMOS area and an NMOS area; forming a germanium-containing channel area on the substrate of the PMOS area; a step of forming a high dielectric layer on the substrate; forming a threshold voltage control layer including lanthanide on the high dielectric layer of the NMOS area; forming a first titanium nitride on the threshold voltage control layer and the high dielectric layer of the PMOS area; forming an inhibiting oxidation layer containing silicon on the first titanium nitride of the NMOS area; forming a second titanium nitride on the first titanium nitride of the NMOS area; forming a first gate stack including the high dielectric layer, the first titanium nitride, and the second titanium nitride on the substrate of the PMOS area; and forming a second gate stack including the high dielectric layer, threshold voltage control layer, the first titanium nitride, and the inhibiting oxidation layer on the substrate of the NMOS area. |
申请公布号 |
KR20150051445(A) |
申请公布日期 |
2015.05.13 |
申请号 |
KR20130132918 |
申请日期 |
2013.11.04 |
申请人 |
SK HYNIX INC. |
发明人 |
JI, YUN HYUCK;JOO, MOON SIG;JANG, SE AUG;LEE, SEUNG MI;KIM, HYUNG CHUL |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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