发明名称 High voltage tolerant input/output circuit
摘要 A high voltage tolerant I/O circuit of an electronic device is disclosed, including a voltage reducing circuit, a first node, a first transistor, a second transistor, and a control logic. The voltage reducing circuit is coupled with a signal pad and utilized for generating a reduced voltage according to an external voltage. When an internal voltage generated by an internal circuit of the electronic device is greater than the reduced voltage, the first node outputs the internal voltage as a first voltage. When the internal voltage is less than the reduced voltage, the first node outputs the reduced voltage as the first voltage. The first transistor is coupled with the signal pad and the first node. The second transistor is coupled with a second terminal of the first transistor and a fixed-voltage terminal. The control logic operates according to the first voltage to control switching operations of the second transistor.
申请公布号 US9030247(B2) 申请公布日期 2015.05.12
申请号 US201313846235 申请日期 2013.03.18
申请人 Alchip Technologies, Ltd. 发明人 Su Wen-Hong
分类号 H03K5/08;H03K19/003;H03K19/0185 主分类号 H03K5/08
代理机构 Birch, Stewart, Kolasch & Birch, LLP 代理人 Birch, Stewart, Kolasch & Birch, LLP
主权项 1. A high voltage tolerant I/O circuit for use in an electronic device comprising a signal pad and an internal circuit, the I/O circuit comprising: a voltage reducing circuit, coupled with the signal pad and configured to operably generate a reduced voltage according to an external voltage transmitted from the signal pad; a first node, coupled with an output terminal of the voltage reducing circuit and configured to operably provide a first voltage; a first switch coupled between the first node and an internal voltage generated by the internal circuit; a control circuit, coupled with a control terminal of the first switch and configured to operably turn on the first switch when the internal voltage rises to a first reference voltage, and to operably turn off the first switch when the internal voltage declines to a second reference voltage; a first transistor, wherein a first terminal of the first transistor is coupled with the signal pad, and a control terminal of the first transistor is coupled with the first node; a second transistor, wherein a first terminal of the second transistor is coupled with a second terminal of the first transistor, and a second terminal of the second transistor is coupled with a fixed-voltage terminal; and a control logic, coupled with the internal voltage and a control terminal of the second transistor and configured to operate according to the internal voltage to control switching operations of the second transistor; wherein the external voltage is greater than the internal voltage, the first reference voltage, and the second reference voltage, and the first reference voltage is less than the second reference voltage; wherein the control circuit comprises: a second switch coupled between a second voltage and the control terminal of the first switch; a first comparing circuit, coupled with a control terminal of the second switch and configured to operably compare the internal voltage with the first reference voltage to control switching operations of the second switch; a third switch coupled between a third voltage and the control terminal of the first switch; and a second comparing circuit, coupled with a control terminal of the third switch and configured to operably compare the internal voltage with the second reference voltage to control switching operations of the third switch.
地址 Taipei TW