| 发明名称 | Resistive switching memories | ||
| 摘要 | A memory cell includes a first resistive switching device having a first terminal and a second terminal, a switching device having a first terminal and a second terminal, and an access device having a first access terminal and a second access terminal. The first access terminal is coupled to the first terminal of the first resistive switching device and the first terminal of the switching device. | ||
| 申请公布号 | US9029829(B1) | 申请公布日期 | 2015.05.12 |
| 申请号 | US201213462659 | 申请日期 | 2012.05.02 |
| 申请人 | Adesto Technologies Corporation | 发明人 | Echeverry Juan Pablo Saenz;Kamalanathan Deepak |
| 分类号 | H01L27/24;G11C5/06 | 主分类号 | H01L27/24 |
| 代理机构 | Slater & Matsil, L.L.P. | 代理人 | Slater & Matsil, L.L.P. |
| 主权项 | 1. A memory cell comprising: a first resistive switching device having a first terminal and a second terminal; a switching device having a first terminal and a second terminal; and an access device having a first access terminal and a second access terminal, the first access terminal being coupled to the first terminal of the first resistive switching device and the first terminal of the switching device, wherein the memory cell is a memory having two-states comprising a high impedance state and a low impedance state, and wherein the first resistive switching device and the switching device provide redundancy to the memory cell. | ||
| 地址 | Sunnyvale CA US | ||