发明名称 Semiconductor integrated circuit device
摘要 In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.
申请公布号 US9029917(B2) 申请公布日期 2015.05.12
申请号 US201414276940 申请日期 2014.05.13
申请人 Socionext Inc. 发明人 Taniguchi Koichi;Maede Masato
分类号 H01L27/02;H01L27/092;H01L23/544 主分类号 H01L27/02
代理机构 McDermott Will & Emery LLP 代理人 McDermott Will & Emery LLP
主权项 1. A semiconductor integrated circuit device, comprising: a semiconductor chip including an internal circuit and a plurality of I/O cells, wherein: the plurality of I/O cells are provided on a periphery area of the semiconductor chip, each of the plurality of I/O cells includes a first region to which first voltage is supplied and a second region to which second voltage is supplied, wherein the second voltage is lower than the first voltage, the first region including a protective circuit for protecting the internal circuit from discharge of static electricity, the first region is disposed closer to an outermost edge of the semiconductor chip than the second region, each of the plurality of I/O cells has a corresponding electrode pad overlapping the I/O cell in plane view and connected to the corresponding protective circuit, electrode pads of the plurality of I/O cells are arranged on a first line and a second line, the first line being disposed closer to the outermost edge of the semiconductor chip than the second line, and side edges of the electrode pads disposed on the first line, which are parallel to and closest to the outermost edge of the semiconductor chip, are disposed on a substantially same line as side edges of the plurality of I/O cells, which are parallel to and closest to the outermost edge of the semiconductor chip.
地址 Kanagawa JP