| 发明名称 | Integrated circuit layout | ||
| 摘要 | An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV. | ||
| 申请公布号 | US9030025(B2) | 申请公布日期 | 2015.05.12 |
| 申请号 | US201313834495 | 申请日期 | 2013.03.15 |
| 申请人 | IPEnval Consultant Inc. | 发明人 | Huang Chao-Yuan;Ho Yueh-Feng;Yang Ming-Sheng;Chen Hwi-Huang |
| 分类号 | H01L23/48 | 主分类号 | H01L23/48 |
| 代理机构 | Kamrath IP Lawfirm, P.A. | 代理人 | Kamrath Alan D.;Kamrath IP Lawfirm, P.A. |
| 主权项 | 1. An integrated circuit layout, comprising: a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV); a through silicon via (TSV) configured to couple operational signals (signal TSV); a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) surrounding the VDD TSV and the signal TSV; and one or more backside redistribution lines (RDLs) of the same level connecting the VSS TSVs together to form a web-like heat dissipating structure completely surrounding the VDD TSV and the signal TSV, wherein the one or more backside RDLs of the same level run along a first direction and a second direction different from the first direction. | ||
| 地址 | Hsinchu TW | ||