Semiconductor memory device controlling refresh cycle, memory system, and method of operating the semiconductor memory device

摘要

A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.

主权项

1. A semiconductor memory device comprising:
a memory cell array comprising a plurality of memory cells; a refresh control circuit configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all memory cells of the semiconductor memory device, m being a natural number greater than 1; an address counter configured to generate counting signals for refreshing memory cells in response to the m refresh control signals; and an address converter configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal, wherein the address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.