Semiconductor device having well regions with opposite conductivity

摘要

A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.

主权项

1. A semiconductor device comprising:
(a1) a first transistor coupled between a first potential and a first node; (a2) a second transistor coupled between the first node and a second potential lower than the first potential; (a3) a third transistor coupled between the first potential and a second node; (a4) a fourth transistor coupled between the second node and the second potential; (b1) a first active region which is surrounded by an element isolation region and in which the first transistor is located; (b2) a second active region which is surrounded by the element isolation region and in which the second transistor is located; (c) an insulating layer placed below the first active region and the second active region; (d1) a first semiconductor region placed below the first active region via the insulating layer and surrounded by the element isolation region; (d2) a second semiconductor region placed below the second active region via the insulating layer and surrounded by the element isolation region; (e1) a third semiconductor region placed below the first semiconductor region and at least partially extending to a position deeper than the element isolation region; and (e2) a fourth semiconductor region placed below the second semiconductor region and at least partially extending to a position deeper than the element isolation region, wherein the first semiconductor region is coupled to the gate electrode of the first transistor, wherein the second semiconductor region is coupled to the gate electrode of the second transistor; wherein the third semiconductor region is a region having a conductivity type opposite to that of the first semiconductor region and coupled to the first potential, and wherein the fourth semiconductor region is a region having a conductivity type opposite to the second semiconductor region and coupled to the second potential.