| 主权项 |
1. A direct memory access (DMA) engine processing transfer requests of a data processing system, comprising:
a command processor adapted to receive and interpret transfer requests of the data professing system, transfer requests being received by the command processor through a set of command FIFO registers respectively servicing requests of different transfer priorities; a transfer memory connected to the command processor and having, for each of the transfer requests, data fields including transfer priority and transfer deadline; a transaction dispatcher connected to the transfer memory and having read, read response and write engines adapted to handle command and data octet transfers through a set of read and write FIFO registers to and from a DRAM controller and a global bus interface in accord with transfer requests interpreted by the command processor; and a channel scanner connected to the transfer memory and having a deadline engine and a transaction controller, the deadline engine adapted to determine a transfer urgency, and the transaction controller adapted to schedule among multiple transfer requests interpreted by the command processor based on the determined transfer urgency of the respective transfer requests so as to control the engines of the transaction dispatcher, wherein the transfer urgency is based on both a transfer deadline and a transfer priority, such that higher priority transfers have higher urgency, and equal priority transfers with earlier deadlines have higher urgency, the transfer priority being based on a hardness representing a penalty for missing a deadline and is also assigned to zero-deadline transfer requests for which there is a penalty no matter how early the transfer completes and the penalty increases with completion time of the transfer, the transaction controller scheduling requested transfers such that requests of the highest transfer priority are allocated to a largest time slice and those of lower transfer priorities are allocated to at least one other smaller time slice, the transaction controller adapted to preempt processing of a current transfer by the transaction dispatcher when a time slice expires and a higher urgency request has been received. |
