Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric

摘要

Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.

主权项

1. A method of fabricating a field-effect transistor (FET) device, comprising the steps of:
providing a silicon-on-insulator (SOI) wafer having a SOI layer over a buried oxide (BOX); patterning nanowires and pads in the SOI layer with the pads attached at opposite ends of the nanowires in a ladder-like configuration; recessing the BOX under the nanowires; forming at least one dummy gate comprising a patternable dielectric over the recessed BOX and surrounding a portion of each of the nanowires, wherein the at least one dummy gate is formed by exposure of the patternable dielectric and removal of unexposed portions of the patternable dielectric using a developer, and wherein the portions of the nanowires surrounded by the at least one dummy gate comprise a channel region of the FET and wherein the pads and portions of the nanowires extending out from the at least one dummy gate comprise source and drain regions of the FET; depositing a chemical mechanical polishing (CMP) stop layer over the at least one dummy gate and over the source and drain regions; depositing a dielectric film over the CMP stop layer; planarizing the dielectric film using CMP to expose the at least one dummy gate; partially removing the at least one dummy gate enough to release the nanowires in the channel region such that the nanowires are suspended in the channel region but a portion of the at least one dummy gate remains on the BOX below the nanowires; and replacing the at least one dummy gate that has been partially removed with a gate conductor material.