发明名称 Nonvolatile semiconductor storage device
摘要 According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a cell well in a row direction and a column direction in a matrix; word lines which select the memory cell in the row direction; bit lines which select the memory cell in the column direction; a sense amplifier which determines a value stored in the memory cell based on a potential of the bit line; a peripheral transistor in the memory cell array which is arranged in the periphery of the memory cell array; and an enhancement type transistor which drives a gate of the peripheral transistor.
申请公布号 US9030880(B2) 申请公布日期 2015.05.12
申请号 US201313847085 申请日期 2013.03.19
申请人 Kabushiki Kaisha Toshiba 发明人 Iwai Makoto
分类号 G11C16/24;G11C16/26;G11C16/14;G11C16/04;G11C16/34 主分类号 G11C16/24
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A nonvolatile semiconductor storage device comprising: a memory cell array where memory cells are arranged in a cell well in a row direction and a column direction in a matrix; word lines which select the memory cell in the row direction; bit lines which select the memory cell in the column direction; a peripheral transistor which is arranged in the cell well; a depletion type transistor which drives a gate of the peripheral transistor; an enhancement type transistor which is connected in series to the depletion type transistor; and a gate control circuit which controls gate potential voltages of the depletion type transistor and the enhancement type transistor, wherein the gate control circuit controls the gate potential voltages of the depletion type transistor and the enhancement type transistor so that the enhancement type transistor is turned off during an erasing period of the memory cell.
地址 Tokyo JP