发明名称 Adjusting program and erase voltages in a memory device
摘要 A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string.
申请公布号 US9030874(B2) 申请公布日期 2015.05.12
申请号 US201414150568 申请日期 2014.01.08
申请人 Micron Technology, Inc. 发明人 Aritome Seiichi
分类号 G11C16/04;G11C16/16;H01L27/02;H01L27/115 主分类号 G11C16/04
代理机构 Fletcher Yoder, P.C. 代理人 Fletcher Yoder, P.C.
主权项 1. A memory array comprising: a first select gate; a first edge cell arranged directly adjacent to and not in contact with the first select gate; a second select gate; and a second edge cell arranged directly adjacent to the second select gate, wherein during an erase operation, the first edge cell is configured to receive a first erase voltage and the second edge cell is configured to receive a second erase voltage different from the first erase voltage.
地址 Boise ID US