Channel diagnostic system for sent receiver

摘要

A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.

主权项

1. A system for performing at least one diagnostic check on a first data message transmitted from a sensor unit to a receiver unit associated with an engine control unit (ECU), wherein the sensor unit operates based on a sensor unit clock signal, comprising:
a nibble counter for receiving the first data message and determining a nibble length of at least one nibble of the first data message based on a compensated receiver clock signal, wherein the compensated receiver clock signal is substantially identical to the sensor unit clock signal; an accumulator, connected to the nibble counter, for receiving the nibble length from the nibble counter and adding one or more nibble lengths to obtain a length of the first data message; and a pause pulse diagnostic circuit, connected to the accumulator, for performing the at least one diagnostic check on the first data message after a pause pulse is detected in the first data message and generating a diagnostic check signal that indicates at least one of pass and fail status of the first data message, wherein the pause pulse diagnostic circuit comprises:
a subtractor circuit, connected to the accumulator, for determining a difference between the length of the first data message and a length of a second data message, wherein the second data message is received immediately before the first data message;a modulus calculator circuit, connected to the subtractor circuit, for determining an absolute value that is a modulus of the difference between the lengths of the first and second data messages;a bit shifter circuit, connected to the modulus calculator circuit, for shifting the absolute value by a predetermined bit count to obtain a shifted absolute value;an adder circuit, connected to the accumulator, for determining a sum of the length of the first data message and a predetermined value; anda comparator circuit, connected to the bit shifter circuit and the adder circuit, for comparing the shifted absolute value with the sum of the length of the first data message and the predetermined value, and generating the diagnostic check signal.