Level shifter with output spike reduction

摘要

A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

主权项

1. A level shifter apparatus having at least one level-shifted final output ranging from about a positive supply rail voltage VDD in a first state to about a negative supply rail voltage VSS in a second state, either of the two states adapted to be selected based on value of an input control signal operating within a range substantially different from the range between the negative supply rail voltage VSS and the positive supply rail voltage VDD, the level shifter comprising:
a) a first inverting circuit and a second inverting circuit configured to output a first inverter output voltage and a second inverter output voltage, respectively, to a first final output circuit, the first final output circuit configured to produce a level-shifted final output based on the first inverter output voltage and the second inverter output voltage, wherein:
i) the first inverter output voltage is within a range from about a common voltage to about the positive supply rail voltage VDD,ii) the second inverter output voltage is within a range from about the common voltage to about the negative supply rail voltage VSS, andiii) in either of the first and second states of the level-shifted final output, one of the inverter output voltages is either at about the negative supply rail voltage VSS or at about the positive supply rail voltage VDD and the other inverter output voltage is at about the common voltage; and b) a first transition control circuitry and a second transition control circuitry connected with the first inverting circuit and the second inverting circuit, respectively, each of the transition control circuitries configured to delay a transition of a corresponding inverter output voltage from around the common voltage toward either about the negative supply rail voltage VSS or about the positive supply rail voltage VDD until the other inverter output voltage has significantly transitioned from either about the negative supply rail voltage VSS or about the positive supply rail voltage VDD toward the common voltage.