Data output timing control circuit for semiconductor apparatus

摘要

A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.

主权项

1. A data output timing control circuit for a semiconductor apparatus comprising:
a delay amount calculation unit configured to subtract a code value of a counting code, which is obtained by counting a variable delay amount and a data output path delay amount based on an external clock that has been delayed as much as a variable delay amount, from a code value of data output delay information and output the result of subtraction as a delay control code; and a phase adjustment unit configured to receive and delay a read command by as much as the variable delay amount, shift a phase of a delayed read command by as much as a code value of the delay control code, and output the result of the shift as an output enable flag signal, wherein the phase adjustment unit shifts the phase of the delayed read command by as much as the code value of the control code in sequential synchronization with a plurality of delayed clocks obtained by delaying a delay locked loop (DLL) clock by as much as predetermined delay amounts, respectively.