| 摘要 |
PROBLEM TO BE SOLVED: To implement an efficient parallel data communication receiver circuit that also restores effective data bits just after an alignment marker (AM) of a head lane among a plurality of lanes in reception start.SOLUTION: The parallel data receiver circuit includes: a deskew part 41 for removing skew between lanes on the basis of an AM of parallel data received by a plurality of lanes Lane 0 to 3; a parallel/serial conversion part 42 for converting the parallel data into serial data; a descramble part 43 that performs descramble processing for restoring parallel/serial conversion data; and a control part 60 that holds data of a plurality of lanes, detects an order of the plurality of lanes on the basis of the AM, identifies data just after the AM of the head lane and outputs data just before the AM of the final lane to the descramble part. The descramble part performs the descramble processing after switching a part of data from the parallel/serial conversion part and preceding data. |
