| 摘要 |
<p>PROBLEM TO BE SOLVED: To efficiently verify whether or not layout design is carried out exactly as in a circuit diagram.SOLUTION: A layout verification device 1 combines elements of the same kind included in a circuit diagram and having the relationship of a series connection and creates a net list for reference. Next, the layout verification device 1 executes an LVS using a net list for the circuit diagram and the net list for reference to identify a non-matching place in many-to-one instance information, and executes the LVS using a net list for layout and the net list for reference to identify a non-matching place in many-to-one instance information. Then, by correlating one instance information about each of these non-matching places to each other, the layout verification device 1 correlates a plurality of pieces of instance information about each to each other and identifies a dividing manner for elements in layout with respect to elements in the circuit diagram.</p> |
