METHODS OF FORMING GATE STRUCTURES WITH MULTIPLE WORK FUNCTIONS AND THE RESULTING PRODUCTS

摘要

One illustrative method disclosed herein includes removing sacrificial gate structures for NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, forming a high-k gate insulation layer in the NMOS and PMOS gate cavities, forming a lanthanide-based material layer on the high-k gate insulation layer in the NMOS and PMOS gate cavities, performing a heating process to drive material from the lanthanide-based material layer into the high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of the NMOS and PMOS gate cavities, and forming gate electrode structures above the lanthanide-containing high-k gate insulation layer in the NMOS and PMOS gate cavities.

主权项

1. A method of forming replacement gate structures for an NMOS transistor and a PMOS transistor, comprising:
performing at least one etching process to remove a sacrificial gate structure for said NMOS transistor and a sacrificial gate structure for said PMOS transistor to thereby define an NMOS gate cavity and a PMOS gate cavity; depositing a high-k gate insulation layer in said NMOS gate cavity and in said PMOS gate cavity; prior to performing any heating processes on said as-deposited high-k gate insulation layer in either of said NMOS or PMOS gate cavities, performing a deposition process to deposit a lanthanide-based material layer on said as-deposited high-k gate insulation layer that is positioned within said NMOS and PMOS gate cavities, wherein said as-deposited lanthanide-based material layer comprises lanthanum; after depositing said lanthanide-based material layer, performing at least one heating process to drive material from said as-deposited lanthanide-based material layer into said as-deposited high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of said NMOS and PMOS gate cavities; and performing at least one process operation to form a first gate electrode structure above said lanthanide-containing high-k gate insulation layer in said NMOS gate cavity and a second gate electrode structure above said lanthanide-containing high-k gate insulation layer in said PMOS gate cavity.