发明名称 |
RECONFIGURABLE CIRCUIT, STORAGE DEVICE, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE |
摘要 |
A reconfigurable circuit suitable for a redundant circuit of a storage device is provided. A programmable logic element (PLE) includes k logic circuits (e.g., XNOR circuits), k configuration memories (CM), and another logic circuit (e.g., an AND circuit) to which the outputs of the k logic circuits are input. The output of the AND circuit represents whether k input data of the PLE all correspond to configuration data stored in the k CMs. For example, when the address of a defective block in the storage device is stored in the CM and address data of the storage device the access of which is requested is input to the PLE, whether the defective block is accessible can be determined from the output of the AND circuit. |
申请公布号 |
US2015123704(A1) |
申请公布日期 |
2015.05.07 |
申请号 |
US201414526720 |
申请日期 |
2014.10.29 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
Kurokawa Yoshiyuki |
分类号 |
H03K19/003;H03K19/20;H03K19/0175 |
主分类号 |
H03K19/003 |
代理机构 |
|
代理人 |
|
主权项 |
1. A reconfigurable circuit comprising:
at least one programmable logic element, the programmable logic element comprising:
first to k-th logic circuits, where k is an integer of two or more;first to k-th configuration memories;a programmable look-up table;a register; anda multiplexer, wherein the register is configured to store data output from the programmable look-up table, wherein the multiplexer is configured to select and output data output from the programmable look-up table or data output from the register, wherein the first to k-th logic circuits are each configured to perform an operation of an exclusive-NOR of first to k-th data and first to k-th configuration data output from the first to k-th configuration memories, respectively, and output an operation result as (k+1)th to 2k-th data, and wherein the programmable look-up table is configured to perform a logical operation of the (k+1)th to 2k-th data and (2k+1)th data and output an operation result as (2k+2)th data. |
地址 |
Atsugi-shi JP |