发明名称 TEST, VALIDATION, AND DEBUG ARCHITECTURE
摘要 An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
申请公布号 US2015127983(A1) 申请公布日期 2015.05.07
申请号 US201013997182 申请日期 2010.12.23
申请人 Trobough Mark B.;Tiruvallur Keshavan K.;Prudvi Chinna B.;Iovin Christian E.;Grawrock David W.;Nejedlo Jay J.;Kabadi Ashok N.;Goff Travis K.;Halprin Evan J.;Udawatta Kapila B.;Foo Jiun Long;Cheah Wee Hoo;Liew Vui Yong;Gopal Selvakumar Raja;Lee Yuen Tat;Samaan Samie B.;Killpack Kip C.;Dobler Neil;Hakim Nagib Z.;Meyer Briar;Penner William H.;Baudrexl John L.;Wunderlich Russell J.;Grealish James J.;Markley Kyle;Storey Timothy S.;McConnell Loren J.;Cool Lyle E.;Kataria Mukesh;Mohammed Rahima K.;Zheng Tieyu;Xia Yi Amy;Sahan Ridvan A.;Ramadorai Arun R.;Patra Priyadarsan;Parks Edwin E.;Davare Abhijit;Gopal Padmakumar;Querbach Bruce;Gartler Hermann W.;Drescher Keith;Salem Sanjay S.;Florey David C. 发明人 Trobough Mark B.;Tiruvallur Keshavan K.;Prudvi Chinna B.;Iovin Christian E.;Grawrock David W.;Nejedlo Jay J.;Kabadi Ashok N.;Goff Travis K.;Halprin Evan J.;Udawatta Kapila B.;Foo Jiun Long;Cheah Wee Hoo;Liew Vui Yong;Gopal Selvakumar Raja;Lee Yuen Tat;Samaan Samie B.;Killpack Kip C.;Dobler Neil;Hakim Nagib Z.;Meyer Briar;Penner William H.;Baudrexl John L.;Wunderlich Russell J.;Grealish James J.;Markley Kyle;Storey Timothy S.;McConnell Loren J.;Cool Lyle E.;Kataria Mukesh;Mohammed Rahima K.;Zheng Tieyu;Xia Yi Amy;Sahan Ridvan A.;Ramadorai Arun R.;Patra Priyadarsan;Parks Edwin E.;Davare Abhijit;Gopal Padmakumar;Querbach Bruce;Gartler Hermann W.;Drescher Keith;Salem Sanjay S.;Florey David C.
分类号 G06F11/273 主分类号 G06F11/273
代理机构 代理人
主权项 1. An apparatus comprising: one or more testing hooks adapted to provide test information; and abstraction logic adapted to abstract the one or more hardware testing hooks from the software layer and to provide an interface to a software layer, the interface being adapted to provide services associated with the one or more hardware testing hooks.
地址 Olympia WA US