发明名称 VERTICAL NITRID-BASED TRANSISTOR HAVING CURRENT BLOCKING LAYER AND METHOD OF FABRICATING THE SAME
摘要 In a method of fabricating a vertical nitride-based transistor according to an embodiment, a nitride-based first semiconductor layer doped with a first type, an insulating current blocking layer, a nitride-based second semiconductor layer doped with a second type, and a nitride-based third semiconductor layer doped with a third type are successively formed on a growth substrate. A first trench which is extended from the third semiconductor layer to the inside of the first semiconductor layer is formed. A nitride-based fourth first trench layer doped with a first type which is filled in the first trench is formed. A second trench is formed in the fourth semiconductor. A gate electrode is formed in the second trench. A source electrode which is electrically connected to the third semiconductor layer or the fourth semiconductor layer is formed. A drain electrode which is electrically connected to the first semiconductor layer is formed.
申请公布号 KR20150047818(A) 申请公布日期 2015.05.06
申请号 KR20130127760 申请日期 2013.10.25
申请人 SEOUL SEMICONDUCTOR CO., LTD. 发明人 TAKEYA MOTONOBU
分类号 H01L21/336;H01L29/78 主分类号 H01L21/336
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