| 摘要 |
A memory or CPU die 106 is embedded in a coreless substrate, wherein a mold compound surrounds the die, and the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands. The package is manufactured on a carrier substrate that is removed after the mold compound is formed. |
