Method for performing built-in self-tests and electronic circuit

摘要

A method and apparatus for performing an array built-in self-test (ABIST) on an electronic circuit 100 comprising a memory 110 with two or more memory arrays 111-115 and two or more array built-in self-test engines 116-120, each engine associated with a different memory array 111-115, and each engine associated with a programmable delay unit DU1-DU5, preferably a dedicated separate delay unit. The disclosed method comprises the following steps: determine at least one delay value (dn) corresponding to an array built-in self-test engine 116-120 and the delay value (dn) depending on the execution time (tdn) for testing the memory array; provide at least one delay value (dn) to the programmable delay unit DU1-DU5; the method continues by delaying the start of the ABIST engine 116-120 depending on the respective delay value (dn). The delay value (dn) may be determined from the test duration (tdn) of an associated memory cell and the maximum of all test durations (tdmax), for example the difference between tdmax and tdn.. The delay values (dn) may also be chosen such that some or all sets of ABIST engines start processing at different times so as to avoid fluctuations and disturbances in supply currents. Preferably the delay times maybe chosen such that all of the ABIST engines terminate or stop at the same point in time (tend) (figure 5). The termination point is monitored by a dedicated monitoring unit. The programmable delay unit(s) DU1-DU5 may be adapted to generate a start signal after expiry of the delay value (dn) in order to start processing of the associated ABIST engine.