发明名称 |
HIGH-PERFORMANCE CACHE SYSTEM AND METHOD |
摘要 |
A method for facilitating operation of a processor core is provided. The method includes: examining instructions being filled from a second instruction memory to a third instruction memory, extracting instruction information containing at least branch information and generating a stride length of base register corresponding to every data access instruction; creating a plurality of tracks based on the extracted instruction; filling at least one or more instructions that are likely to be executed by the processor core based on one or more tracks from the plurality of tracks from a first instruction memory to the second instruction memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second instruction memory to the third instruction memory; calculating possible data access address of the data access instruction to be executed next time based on the stride length of the base register. |
申请公布号 |
EP2867778(A1) |
申请公布日期 |
2015.05.06 |
申请号 |
EP20130809284 |
申请日期 |
2013.06.26 |
申请人 |
SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD |
发明人 |
LIN, KENNETH, CHENGHAO |
分类号 |
G06F12/08;G06F9/345;G06F9/38 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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