Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array

摘要

Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

主权项

1. A method of accessing a plurality of cross-point memory cells, the method comprising:
biasing a first address line of a three-dimensional array of memory cells; biasing a plurality of second address lines extending across the first address line; and biasing another first address line extending parallel to the first address line, the three-dimensional array of memory cells having a first plurality of memory cells in a first plane between the first address line and the plurality of second address lines, and a second plurality of memory cells in a second plane between the plurality of second address lines and the another first address line, wherein each of the memory cells of the first and second pluralities of memory cells are configured to store a first data value therein if a positive voltage is across the respective memory cell, and to store a second data value therein if a negative voltage is across the respective memory cell, wherein biasing a first address line, biasing a plurality of second address lines, and biasing another first address line occur according to a biasing scheme that causes at least one memory cell of the first plurality of memory cells in the first plane and at least one memory cell of the second plurality of memory cells in the second plane having the same data value to be accessed within a single clock cycle while at least one other memory cell of the first plurality of memory cells in the first plane and at least one other memory cell of the second plurality of memory cells in the second plane are not accessed within the single clock cycle.