| 发明名称 |
Method and apparatus for designing a system on multiple field programmable gate array device types |
| 摘要 |
A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer. |
| 申请公布号 |
US9026967(B1) |
申请公布日期 |
2015.05.05 |
| 申请号 |
US201414245228 |
申请日期 |
2014.04.04 |
| 申请人 |
Altera Corporation |
发明人 |
Perry Steven |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
Cho L. |
| 主权项 |
1. A method for designing a system to be implemented on a target device, comprising:
identifying a number of partitions required for an adder from resources on the target device and from a timing requirement; and adding pipelined delays to be implemented with the adder to form a partitioned adder, wherein at least one of the identifying and adding is performed by a processor. |
| 地址 |
San Jose CA US |
