On-chip interferers for standards compliant jitter tolerance testing

摘要

Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.

主权项

1. An integrated circuit for communicating signals with predetermined jitter, comprising:
an output queue having a signal input, a clock input and an output, wherein the output queue is configured to output a signal received at the signal input according to a clock signal received at the clock input; a phase adjuster configured to receive a phase adjustment input signal, and generate the clock signal by shifting the phase adjustment input signal according to a received phase control signal, and output the clock signal to the clock input of the output queue; a jitter test module configured to receive a jitter input signal and generate a jitter control signal based on the jitter input signal; and a combiner configured to produce the phase control signal by combining the jitter control signal with a transmit control signal.