发明名称 |
Sequential burn-in test mechanism |
摘要 |
A method includes performing a burn-in test on an integrated circuit (IC) by removing power from a first component block within the IC and applying a maximum burn-in voltage and temperature to a second component block within the IC. |
申请公布号 |
US9024647(B2) |
申请公布日期 |
2015.05.05 |
申请号 |
US201213600474 |
申请日期 |
2012.08.31 |
申请人 |
Intel Corporation |
发明人 |
Vassighi Arman;Zia Victor |
分类号 |
G01R31/10;G01R31/28;G01R31/317 |
主分类号 |
G01R31/10 |
代理机构 |
Blakely, Sokoloff, Taylor & Zafman LLP |
代理人 |
Blakely, Sokoloff, Taylor & Zafman LLP |
主权项 |
1. An integrated circuit (IC) comprising:
a first component block; a second component block; and a power control unit (PCU) coupled to the first and second component blocks to perform a burn-in test of the IC by removing power from the second component block and applying a maximum burn-in voltage and temperature to the first component block, wherein performing the burn-in test of the IC further comprises removing power from the first component block and applying the maximum burn-in voltage and temperature to the second component block; a first gate transistor coupled between the first component block and the PCU; and a second gate transistor coupled between the second component block and the PCU. |
地址 |
Santa Clara CA US |