Three-dimensional memory comprising an integrated intermediate-circuit die

摘要

The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least an integrated intermediate-circuit die comprising both a read/write-voltage generator (VR/VW-generator) and an address/data translator (A/D-translator). The intermediate-circuit die performs voltage, address and/or data conversion between the 3D-M core region and the host. Discrete 3D-M support multiple 3D-array dies.

主权项

1. A discrete three-dimensional memory (3D-M), comprising:
a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels; an intermediate-circuit die comprising at least a first portion of a read/write-voltage generator and at least a second portion of an address/data translator, wherein said read/write-voltage generator provides said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, and said address/data translator converts at least an address and/or data between a host and said 3D-array die; wherein said first portion of said read/write-voltage generator and said second portion of said address/data translator are absent from said 3D-array die; said 3D-array die comprises more back-end layers than said intermediate-circuit die; and, said 3D-array die and said intermediate-circuit die are separate dice.