发明名称 |
Power quad flat no-lead (PQFN) package |
摘要 |
Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes. |
申请公布号 |
US9024420(B2) |
申请公布日期 |
2015.05.05 |
申请号 |
US201314076467 |
申请日期 |
2013.11.11 |
申请人 |
International Rectifier Corporation |
发明人 |
Fernando Dean;Barbosa Roel |
分类号 |
H01L23/495;H01L23/00;H01L23/31 |
主分类号 |
H01L23/495 |
代理机构 |
Farjami & Farjami LLP |
代理人 |
Farjami & Farjami LLP |
主权项 |
1. A power quad flat no-lead (PQFN) semiconductor package comprising:
a leadframe comprising a plurality of die pads; a driver integrated circuit (IC) coupled to a top surface of a first die pad of said leadframe; a plurality of vertical conduction power transistors including a first group of vertical conduction power transistors coupled to a top surface of a common die pad of said leadframe and a second group of vertical conduction power transistors individually coupled to respective top surfaces of separate die pads of said leadframe; a top surface electrode of one of said first group of vertical conduction power transistors being electrically connected to a bottom surface electrode of one of said second group of vertical conduction power transistors; at least one wirebond providing direct electrical connection between said driver IC and one of said plurality of vertical conduction power transistors; wherein each of said first die pad, said common die pad and said separate die pads has a separate exposed surface on a bottom surface of said leadframe. |
地址 |
El Segundo CA US |