| 摘要 |
The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data output circuit, and a data receiving circuit. The memory module includes a memory buffer and at least two memory chips. The memory buffer includes a second control circuit, a write circuit, and a read circuit. The advantage of the present invention is that, when data is read or written into the memory chip, especially a DDR4 X4 memory chip, low power consumption of interface data transmission can be achieved through a data bus inversion control line DBI. |
| 主权项 |
1. A data output circuit, comprising:
a check data generation unit, configured to generate a first set of check data according to n1*b pieces of data in n*b pieces of data to be output, and generate a second set of check data according to the remaining n2*b pieces of data in the n*b pieces of data to be output, where n, n1, n2 and b are integer values corresponding to a number of pieces of data, n*b is a numerical multiplication of the n pieces of data and number of the b pieces of data, n1*b is a numerical multiplication of the n1 pieces of data and the b pieces of data, and, n2*b is a numerical multiplication of the n2 pieces of data and the b pieces of data; a first data processing unit, connected to an output end of the check data generation unit, and configured to:
(1) determine first inversion control data corresponding to n pieces of data according to every n pieces of data in the n*b pieces of data to be output;(2) determine first inversion control data corresponding to every n pieces of data in data formed by the first set of check data and the second set of check data from the check data generation unit to be of a second numerical value;(3) when the determined first inversion control data is of a first numerical value, negate n pieces of data to be output corresponding to the first inversion control data and then output the n pieces of negated data; otherwise, directly output the n pieces of data to be output; and(4) output the first inversion control data corresponding to every n pieces of data; and a first data output unit, connected to an output end of the first data processing unit, disposed with a first data bus and a first data bus inversion control line, and configured to output the n*b pieces of data, the first set of check data, the second set of check data, and the first inversion control data from the first data processing unit, wherein every time the n pieces of data are output through the first data bus, the first inversion control data corresponding to the n pieces of data is output through the first data bus inversion control line. |
