Methodology for pattern correction

摘要

The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

主权项

1. A method for pattern correction of an integrated chip design, comprising:
forming an integrated chip (IC) design comprising a graphical representation of an integrated chip having a plurality of main feature shapes; adding a plurality of dummy shapes to the IC design, wherein the plurality of dummy shapes are configured to improve a process window of the IC design; performing an optical proximity correction (OPC) process on the IC design to add assist features to one or more of the plurality of main feature shapes, and on a subset of the plurality of dummy shapes so as to form opc'd dummy shapes having associated assist features and non-opc'd dummy shapes not having associated assist features; operating upon one or more of the plurality of main feature shapes and assist features of the main feature shapes with a first pattern correction process; and operating upon one or more of the plurality of dummy shapes and on assist features of the dummy shapes with a second pattern correction process separate from the first pattern correction process; wherein a computer is used to form the IC design, add the plurality of dummy shapes to the IC design, operate with the first pattern correction process, or operate with the second pattern correction process.