Enforcing strongly-ordered requests in a weakly-ordered processing

摘要

The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.

主权项

1. A weakly-ordered processing system, comprising:
a plurality of memory devices; a plurality of processors, each of the processors configured to generate memory access requests to one or more of the memory devices, each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request; and a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes, wherein the bus interconnect is further configured to enforce ordering constraints for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible to the originating processor.